A transistor, from sand to socket
A switch with no moving parts, made by the trillion, each one built in a few hundred steps on a slice of the purest crystal people make.
The stage follows one chip from step 1, sand, to a tested part in a package. The first few steps, which make the wafer, are 3D scenes. From step 6 the drawing is a cross-section through two transistors, as if the chip had been sawn in half and looked at edge-on under an electron microscope. On the left is an NMOS transistor, which conducts with electrons; on the right a PMOS, which conducts with holes. Wired together they make an inverter, the simplest logic gate and the building block of CMOS, the technology in essentially every processor and memory chip made today. Skip ahead to the finished pair.
1021+transistors made every year, mostly in memory: the most-produced manufactured object by far
336 billionin one Nvidia Rubin GPU (two dies, 2026)
~1,000process steps for a leading-edge chip, over about three months
1.6 nmgate oxide in the process drawn here: about eight atoms
How to use it
- Step through the process with the arrows at the bottom (or your arrow keys), or press play. The timeline is split into making the wafer, the front end (the transistors), contacts, the back end (the wiring), and test and packaging. Steps that happen at the scale of a whole crystal or package switch to a 3D scene.
- After every step the cross-section redraws, and whatever that step added or changed is outlined. The card at the top left says what tool did it, under what conditions, and what is measured afterwards to check it.
- Hover any layer for its name and real size. Drag to pan, scroll or pinch to zoom, double-click to fit. True scale redraws every film at its real thickness: the gate oxide nearly vanishes.
- Explore (top right) lists every topic: the process, the physics of how a transistor switches, how transistors are measured, the toolbox of unit processes, how they shrank over sixty years, and a lab where you can build your own and watch it misbehave.
The process drawn is a planar CMOS flow of the 130–90 nm era (around 2001–2004): shallow trench isolation, twin wells, a polysilicon gate on 1.6 nm of oxynitride, nickel silicide, tungsten contacts and copper wiring. It is the last generation that can be drawn honestly in two dimensions, and nearly every later trick (strain, high-k, FinFETs, nanosheets) is a modification of it, covered under Scaling.
What a transistor does
A voltage on one terminal decides whether current can flow between the other two.
A MOSFET (metal–oxide–semiconductor field-effect transistor) has four terminals. Current flows between the source and the drain through a thin layer at the silicon surface called the channel. Above the channel, separated from it by an insulator a few atoms thick, sits the gate. The fourth terminal, the body, is the silicon underneath.
In an NMOS transistor the body is p-type silicon, full of positive "holes" and nearly empty of free electrons, while the source and drain are n-type, full of electrons. With the gate at zero volts, an electron leaving the source meets a wall of p-type silicon and goes nowhere: the switch is off. Put a positive voltage on the gate and its electric field reaches through the oxide, pushes holes away from the surface and pulls electrons in. Past a certain gate voltage, the threshold voltage, the surface holds more electrons than holes. It has been turned into n-type silicon, an inversion layer, and the source and drain are joined by a conducting channel. The switch is on.
The stage now shows one NMOS transistor, live. Drag the gate and drain voltages at the bottom: below threshold the channel disappears and only a trickle of electrons crosses; above it, electrons stream from source to drain. Raise the drain voltage and the channel thins toward the drain until it pinches off and the current stops growing: saturation.
Billions of these switches, wired so that each one's output drives others' gates, are a processor. The rest of this page is how they are made and why they behave the way they do.
Sand to polysilicon
Silicon is the second most common element in the Earth's crust. Getting it pure enough is the hard part.
The starting point is quartz, silicon dioxide. In a submerged-arc furnace, quartz and carbon (coke, coal, wood chips) are heated to about 2,000 °C and the carbon pulls the oxygen off as CO, leaving metallurgical-grade silicon about 98–99% pure. Most of it goes into aluminium alloys and silicones. For chips, one part per hundred of iron and aluminium is a disaster: a single metal atom in a million can ruin a transistor.
So the silicon is turned into a liquid that can be distilled. Ground and reacted with hydrogen chloride, it becomes trichlorosilane (SiHCl3), which boils at 32 °C. Distillation columns strip out the impurities, each of which forms a chloride with a different boiling point. In the Siemens process, the purified gas flows with hydrogen into a bell-jar reactor over thin silicon rods heated electrically to about 1,100 °C, and silicon deposits back onto them:
SiHCl3 + H2 → Si + 3 HCl
Over several days the rods grow to the thickness of a forearm. Broken up, they are electronic-grade polysilicon: 99.999999999% pure, "eleven nines," with impurities in parts per trillion. It is polycrystalline, though: a jumble of tiny crystals. A transistor needs one perfect crystal.
~98–99%metallurgical-grade silicon from the arc furnace
9–11 nineselectronic-grade polysilicon
~1015boron atoms per cm³ deliberately added later, about one per 50 million silicon atoms
Growing the crystal: the Czochralski method
Dip a seed into the melt and pull it out slowly enough, and the melt freezes onto it as one crystal.
Jan Czochralski found the method by accident in 1916, dipping his pen into a crucible of molten tin instead of his inkwell. Gordon Teal and John Little at Bell Labs used it in 1950 to grow single crystals of germanium and then silicon, and it now makes over 90% of the world's silicon wafers.
Chunks of polysilicon, plus a measured pinch of boron to make the crystal p-type, are melted at 1,414 °C in a quartz crucible held in a graphite susceptor, under argon. A small seed crystal, cut so its atomic planes face a chosen direction (usually ⟨100⟩), is lowered until it touches the melt, then drawn upward while seed and crucible rotate in opposite directions. Atoms in the melt freeze onto the seed in its exact lattice positions. The steps, which you can play on the stage:
The trick that made large crystals perfect is the neck. The thermal shock of touching the seed to the melt creates dislocations, lines of misplaced atoms that would otherwise run the whole length of the crystal. William Dash at General Electric showed in 1959 that pulling a thin neck, only a few millimetres across, lets those dislocations grow out sideways and vanish at the surface. Every crystal since starts with one.
What the melt leaves behind
A dopant does not freeze into the crystal at the concentration it has in the melt. Each has a segregation coefficient k, the ratio of the two: boron's is about 0.8, phosphorus's 0.35. Because most of the dopant stays behind, the melt gets richer as the crystal grows, and so does the crystal. Boron's coefficient is closest to 1, which makes boron-doped wafers the most uniform.
The quartz crucible also slowly dissolves, so Czochralski silicon holds around 1017–1018 oxygen atoms per cm³. That is not all bad: oxygen stiffens the wafer against warping in hot furnaces, and when it clumps into precipitates deep in the wafer they trap stray metal atoms away from the surface, a trick called internal gettering. Crystals for power devices that cannot tolerate oxygen are grown crucible-free by the float-zone method instead.
Deeper: pull rate, defects, and magnets
A growing crystal traps a few of the atomic vacancies and self-interstitials that exist in hot silicon. Which kind wins depends on Voronkov's ratio of pull speed v to the temperature gradient G at the interface: too fast and vacancies cluster into tiny voids (crystal-originated particles, "COPs") that pit the polished surface; too slow and interstitials form dislocation loops. Modern pullers hold v/G in a narrow window to grow "perfect" silicon with neither. For 300 mm crystals, a strong magnetic field (MCZ) also damps convection in the conducting melt, steadying temperature and oxygen.
A 300 mm crystal is about two metres long and weighs a few hundred kilograms; at roughly 0.5–1 mm per minute, the body alone takes a day or two to grow.
Shaping and slicing
A cylinder, a notch, and a saw that cuts a crystal into hundreds of slices at once.
- Crop, grind and notch. The cone-shaped crown and tail are cut off, and the body, grown slightly oversize and a little wavy, is ground to exactly 300 mm. The resistivity is checked along its length, because of the dopant segregation above. An X-ray diffractometer finds the crystal planes, and a small notch is ground along the side to mark one direction (⟨110⟩ on a ⟨100⟩ wafer). Every lithography and wafer-handling tool will later line up to that notch; older, smaller wafers used a flat instead.
- Slice. A multi-wire saw winds a single steel wire, thinner than a hair, hundreds of times around grooved rollers to make a web of parallel strands. The wire runs at about 10 m/s, carrying abrasive slurry or coated with diamond grit, while the ingot, glued to a beam, is pressed slowly down through it. One pass cuts the whole ingot into slices a little under a millimetre thick.
Every cut costs a kerf about as wide as the wire plus its abrasive, roughly 150–200 µm, so about a sixth of the crystal becomes sludge. Grinding and polishing will take more.
The finished wafer
Flat, clean, and almost perfect, before a single transistor is made.
Sawn slices are rough and damaged a few tens of micrometres deep. The edges are ground to a rounded profile (sharp edges chip, and chips become particles). Both faces are ground or lapped flat, the damaged layer is etched away chemically, and both faces are polished. A final chemical-mechanical polish leaves the front surface smooth to a few atoms.
300 mmdiameter, the standard since about 2001 (before that 200 mm)
775 µmthick: enough to survive a thousand handling steps
~10s of nmheight variation across a chip-sized patch of the surface
~10 Ω·cma typical p-type logic substrate: about 1015 boron/cm³
Scaled up so the wafer was ten kilometres across, its surface would vary by about a centimetre over any stretch the size of a city block. It has to be: the lithography tools focus to within a few tens of nanometres. Each wafer is measured for flatness with capacitance gauges, scanned with a laser for particles down to a few tens of nanometres, and sampled for metal contamination. Many logic wafers then get a thin epitaxial layer, a few micrometres of fresh crystal grown on top, which is cleaner than the bulk crystal and can be doped differently from it.
A laser writes an ID near the notch, and the wafer goes into a sealed carrier (a FOUP) with 24 others. It will not see open cleanroom air again until it is diced.
Cleaning, and the starting wafer
The most frequent step in a fab is washing.
The cross-section starts as plain p-type silicon. Before almost every high-temperature step it is cleaned, usually with some descendant of the sequence Werner Kern and David Puotinen published at RCA in 1970:
- SC-1, ammonia and hydrogen peroxide in water at about 70 °C. The peroxide oxidizes the surface and the ammonia slowly etches that oxide, undercutting particles and organic films so they lift off.
- SC-2, hydrochloric acid and peroxide, which dissolves metal contamination: iron, copper, sodium.
- Dilute HF, which strips the thin oxide and leaves bare silicon with its surface bonds capped by hydrogen.
Modern fabs use more dilute chemistries, megasonic agitation and single-wafer spin cleaners, but the logic is the same. The stakes were learned the hard way. In the early 1960s, MOS transistors drifted unpredictably until researchers traced it to sodium ions from handling and furnace parts, which wander through oxide under an electric field and shift the threshold. Cleanrooms, gloves and ultra-pure chemicals made the MOS transistor manufacturable.
ISO class 1–3air near the wafer: at most 10 to 1,000 particles of 0.1 µm or larger per m³
18.2 MΩ·cmresistivity of the ultra-pure water used to rinse, the theoretical limit
Shallow trench isolation
First, fence off where the transistors will go.
Neighbouring transistors share one piece of silicon, so they must be electrically separated, or current would leak sideways between them. Since the late 1990s this is done with shallow trench isolation (STI): trenches about 300 nm deep, filled with oxide, surrounding every "active area" where a transistor will sit. Step through it:
- Pad oxide and nitride. A thin oxide cushions the silicon from the stress of a silicon nitride film, which will serve as a polish stop.
- Lithography. Photoresist is patterned to cover the active areas.
- Trench etch. A plasma etches through the nitride, the oxide and ~300 nm of silicon. The walls are sloped a few degrees so they can be filled without gaps.
- Liner oxidation. A thin grown oxide repairs the etched walls and rounds the top corners. A sharp corner concentrates the gate's field there, forming a parasitic transistor that turns on early.
- Fill. High-density-plasma CVD deposits oxide and sputters it at the same time, so it fills the trenches from the bottom without trapping voids.
- Chemical-mechanical polishing. The excess oxide is polished away. Nitride polishes much more slowly than oxide, so the polish stops on it, leaving oxide only in the trenches.
- Nitride strip. Hot phosphoric acid removes the nitride. The oxide stands a little proud of the silicon, which is deliberate: later wet cleans eat it back.
Before trenches: LOCOS and the bird's beak
From the 1970s to the mid-1990s, isolation was grown, not etched: LOCOS (local oxidation of silicon, developed at Philips around 1970). Nitride masked the active areas and a long oxidation grew thick "field oxide" everywhere else. But oxygen diffuses sideways under the nitride edge, growing a tapered wedge of oxide, the bird's beak, that ate into the active area. At sub-micron dimensions the beaks from two sides nearly met. STI, made practical by chemical-mechanical polishing, replaced it around the 250 nm generation.
Wells: two kinds of silicon on one wafer
NMOS needs a p-type body and PMOS needs an n-type one, side by side.
CMOS needs both transistor types, so the wafer is given regions of each doping, called wells. Each is made by ion implantation: resist covers one side while the other is bombarded with dopant ions, then the roles swap.
- p-well: boron, at several energies. A deep, high-energy implant (hundreds of keV) sets the well; a medium one under the trenches is a channel stop, so no parasitic channel can form beneath the isolation; a shallow one near the surface sets the threshold voltage.
- n-well: phosphorus, the same way, with arsenic or phosphorus near the surface.
- Anneal: heat moves the implanted atoms into lattice sites, where they become electrically active, and repairs the damage the ions did.
Modern wells are retrograde: the implant puts the most dopant deep, not at the surface. That keeps the channel lightly doped (good for mobility) while a heavily doped layer below stops the source and drain depletion regions from reaching each other (punch-through).
Latch-up
Side-by-side wells hide a trap. The n+ source in the p-well, the p-well, the n-well and the p+ source in the n-well form a four-layer pnpn structure: a thyristor. A voltage spike can trigger it, and then it latches into a short circuit from the supply to ground, which can melt the chip. Designs prevent it with frequent well contacts (taps), guard rings, retrograde wells, and heavily doped substrates under epitaxial layers. The taps sit just outside the slice drawn here.
The gate stack
The film that matters most, and the line whose width named the generation.
- Gate oxide. The sacrificial oxide is stripped and a new one grown, in this generation about 1.6 nm: some eight atomic layers. Nitrogen is then added by a plasma, making silicon oxynitride (SiON). The nitrogen stops boron from the p+ gate diffusing through into the channel, and raises the dielectric constant a little.
- Polysilicon. About 100 nm of polycrystalline silicon, deposited from silane at ~620 °C, will be the gate electrode.
- Gate lithography. The most demanding pattern on the chip. Lines are usually printed wider than wanted and narrowed by a trim etch, because the scanner can make a narrow line more reliably than it can print one.
- Gate etch. The plasma must cut 100 nm of polysilicon straight down and then stop dead on 1.6 nm of oxide: a selectivity of more than 100 to 1. An optical sensor watches the plasma's glow change colour as the polysilicon clears.
- Re-oxidation. A few nanometres on the sidewalls repair etch damage and set how far the next implant lands from the gate.
Why so thin? The gate controls the channel through the capacitance of the oxide, Cox = εox/tox. Halve the thickness and the same gate voltage induces twice the charge in the channel: more current, and a tighter grip that keeps the drain from interfering (see short-channel effects). The limit is quantum tunnelling: below about 1.2 nm, electrons leak straight through. That is the story of high-k dielectrics.
Deeper: why polysilicon, and why it had to go
The first MOS gates were aluminium, put down after the source and drain were diffused, which needed a separate, imperfectly aligned mask and left the gate overlapping the junctions. Silicon gates, developed at Fairchild in 1968 (Federico Faggin), could survive the high-temperature steps that come after, so the gate itself could be the mask for the source and drain: the self-aligned gate. Every MOSFET since is self-aligned.
Polysilicon is a semiconductor, though. Under bias the bottom of the gate itself depletes slightly, adding about 0.3–0.4 nm of effective oxide thickness ("poly depletion"), and it interacts badly with hafnium-based dielectrics. From the 45 nm generation, leading-edge gates went back to metal.
Extensions and halos
The gate is the mask: implants land on both sides of it and never under it.
With the gates in place, the source and drain are added in two stages. First, shallow extensions that reach right up to the gate edge. For the NMOS, arsenic at a couple of keV puts the junction only ~20 nm deep; for the PMOS, boron or BF2 below 1 keV. Resist covers the other transistor type each time.
Each extension implant comes with a halo (or pocket): a dose of the opposite dopant fired at a steep tilt (around 30°) from four directions, so it tucks in under the gate edges. Halos locally raise the body doping right where the source and drain depletion regions would otherwise reach toward each other, which holds the threshold voltage up as gates get shorter. They are one of the main tools against short-channel effects in planar transistors.
Why "lightly doped drain"
The extensions began life around 1980 as the lightly doped drain (LDD), a fix for hot carriers. A sharp, heavily doped drain junction concentrates the electric field, and electrons crossing it gain enough energy to be injected into the gate oxide, where they slowly degrade the transistor. Grading the junction with a lighter extension spread the field out. As transistors shrank, the extensions became heavier and shallower, and their job changed to keeping the junctions shallow near the channel.
Spacers: a mask that makes itself
Coat everything evenly, then etch straight down.
- Deposit about 50 nm of silicon nitride that coats tops and vertical sidewalls equally (it is conformal).
- Etch back with a strongly directional plasma that removes material straight down. It clears the flat surfaces in the time it takes to remove 50 nm, but next to each gate the film is as tall as the gate, so a sliver survives on each sidewall.
The result is a spacer of precise width on both sides of every gate, made with no mask and no alignment. It holds the heavy source/drain implant back from the channel, and later keeps the silicide on the gate from shorting to the silicide on the source and drain. The same trick, done twice, is behind self-aligned double and quadruple patterning, which printed the finest lines of the 2010s.
Source, drain, and the activation anneal
A heavy implant, then a second of intense heat.
- NMOS source/drain: arsenic, a few times 1015 ions per cm², outside the spacers. The same implant dopes the NMOS gate n+.
- PMOS source/drain: boron, likewise, making the PMOS gate p+. Doping each gate to match its transistor ("dual poly") puts both thresholds where they should be.
- Spike anneal. A rapid thermal processor ramps the wafer with lamps to about 1,050 °C and straight back down, spending about a second above 1,000 °C.
The anneal has two jobs that pull against each other. Implanted atoms come to rest at random positions, mostly not on lattice sites, where they do nothing electrically; the implant also wrecks the crystal, sometimes turning the surface amorphous. Heat moves dopants onto lattice sites (activation) and regrows the crystal. But heat also makes them diffuse, and a junction that diffuses a few nanometres too far ruins a 50 nm transistor. Each generation's anneals have got shorter: furnace hours, then rapid-thermal seconds, then spikes, then millisecond flash lamps and lasers.
After annealing, a four-point probe on a monitor wafer measures the sheet resistance of the implanted layer, which shows at once whether dose, energy and anneal all landed where they should.
Salicide: metal where silicon is exposed, and nowhere else
Another self-aligned trick, this one chemical.
Doped silicon conducts, but not well: a heavily doped source has a sheet resistance of about 100 Ω per square. Too much of that sits between the wiring and the channel. The fix is to turn the top of every exposed silicon surface into a metal compound.
- Pre-clean and deposit about 10 nm of nickel (with a few percent platinum for stability) over the whole wafer.
- Anneal, strip, anneal. At about 300 °C nickel reacts with silicon wherever they touch: the sources, drains and gate tops. On the oxide and nitride it does nothing. A wet etch then dissolves the unreacted metal, and a second anneal converts the compound to low-resistance nickel monosilicide (NiSi).
The silicide forms exactly where it is needed, with no mask: a self-aligned silicide, or salicide. It cuts the sheet resistance about tenfold. The metal changed with the generations: titanium silicide in the early 1990s, until narrow lines would not transform into its low-resistance phase; cobalt silicide around 180–130 nm; nickel silicide from 90 nm, because it forms at a low temperature and consumes less silicon.
Copper wires, made backwards
Copper cannot be etched into wires, so the wires are carved into the insulator and filled.
Until the late 1990s, chip wiring was aluminium: deposit a film, pattern it, etch away what is not wire, fill around it with oxide. Copper conducts about 40% better and resists electromigration far better, but it has no chlorides volatile enough to etch away in a plasma. IBM's answer, announced in September 1997, was to work in reverse, borrowing the ancient inlay technique called damascening:
- Deposit the insulator: an etch stop, then a low-k film (carbon-doped oxide, k ≈ 3.0 against glass's 3.9). Lower k means less capacitance between neighbouring wires, so signals move faster and use less power.
- Pattern openings where the wires should be.
- Etch trenches down to the tungsten plugs.
- Barrier and seed. Copper diffuses fast through oxide and silicon and kills transistors, so a 5–10 nm tantalum nitride and tantalum barrier lines every trench, followed by a thin copper seed layer that carries the plating current.
- Electroplate. In a copper sulfate bath, organic additives slow plating on the top surface and speed it at the bottom of trenches, so they fill from the bottom up without voids ("superfill").
- Polish and cap. CMP removes the copper and barrier everywhere except the trenches, leaving inlaid wires, and a SiCN cap seals their top surface.
In the slice drawn here, metal 1 makes the inverter. One wire ties the NMOS source to ground, one ties the PMOS source to the supply, and a long wire joins the two drains: that is the output. The two gates are joined by polysilicon just out of the plane of the drawing; that is the input.
Dual damascene: hole and wire in one fill
From metal 2 up, each level is a via and a wire made together.
- Deposit enough low-k film for both a via and a wire.
- Etch twice: narrow via holes down to metal 1, then wider trenches over them (via-first), or the other way round.
- Barrier, seed, plate, polish, exactly as for metal 1, filling via and trench at once.
Wiring levels alternate direction. Here metal 2 runs into the page, so its wires appear as squares, and metal 3 runs across the page again. Some metal 2 squares carry the inverter's signals up; the others are simply other wires passing through.
The whole stack
The transistors are a thin skin; most of a chip's height is wiring.
A logic chip of this era had six to nine copper levels; leading-edge chips now have fifteen or more. The lower levels are thin and dense, for connections between neighbouring transistors. Higher levels are progressively thicker and wider, because long wires need low resistance: the top levels distribute power and clocks across the chip.
Finally the top surface is sealed: aluminium bond pads are deposited on the top copper, a passivation of oxide and silicon nitride covers everything to keep out moisture and sodium, and openings are etched over the pads. Often a polyimide layer goes on top to cushion against the stress of the package.
Wiring got harder as transistors shrank. Shrinking a transistor makes it faster, but shrinking a wire raises its resistance while its capacitance barely falls, so the delay of a fixed length of wire gets worse each generation. By the late 1990s wire delay, not transistor delay, limited clock speed. That drove copper, low-k, and much else (see wires at the limit).
Wafer acceptance test
Before anyone tests a chip, the process is tested.
The narrow lanes between chips, the scribe lines, which the dicing saw will later destroy, are not empty. They hold test structures: single transistors of several sizes, long resistors of each layer, chains of thousands of contacts and vias in series, comb-shaped patterns to catch shorts, capacitors, and ring oscillators. After the wafer is finished, a prober lands needles on their pads at a handful of sites on every wafer (or a sample of wafers), and a parametric analyzer measures dozens of parameters:
Each is checked against spec limits and tracked on statistical process control charts. A wafer outside the limits may be scrapped before a cent is spent testing its chips, and a drift tells engineers which step to look at. The map below simulates one parameter across a wafer for the device chosen in the lab, with a few percent of gate-length variation:
Wafer sort and yield
Every chip on the wafer gets its first test while the wafer is still whole.
A probe card, a board carrying hundreds to tens of thousands of fine needles or MEMS springs laid out to match one chip's pads, touches down on each die in turn while automatic test equipment runs it: checks for opens and shorts, supply current (a defect often shows up as extra leakage), scan patterns that exercise every flip-flop, built-in self-test of the memories, and often speed. Failing memory rows and columns can be swapped for spares on the spot by blowing fuses. Each die gets a pass or a failure bin, and the wafer gets a map.
The fraction that passes is the yield, and it is where a fab's money is made or lost. Random killer defects (a particle, a missing via) land roughly at random, so bigger chips are much more likely to catch one:
Poisson: Y = e−A D0 Murphy: Y = [(1 − e−A D0) / A D0]2
A is the die area and D0 the density of killer defects. A mature process runs near 0.1 per cm² or below; a new one starts several times higher. The steep penalty for large dies is one reason big processors are now split into several smaller chiplets.
Backgrinding and dicing
Thin the wafer, then cut it apart.
- Backgrind. The front is protected with tape and the wafer is ground from the back, from 775 µm down to around 100–300 µm, or under 50 µm for chips that will be stacked. The extra thickness only ever existed to survive handling. A final dry polish removes the grinding damage, which would otherwise make the thin wafer crack.
- Dice. The wafer is mounted on stretchy tape in a metal frame and cut along the scribe lines by a diamond blade a few tens of micrometres thick, spinning at tens of thousands of rpm under a stream of water.
Low-k dielectrics are fragile and delaminate under a saw, so a laser often grooves the wiring layers first. In stealth dicing, a laser focused inside the silicon writes a line of damage without touching the surface; stretching the tape then cracks the wafer cleanly along it, with no kerf and no debris.
Packaging
The package carries power in, signals out, and heat away, and protects a chip that would otherwise crack at a touch.
- Die attach and wire bond. The die is glued or soldered onto a leadframe or substrate. A wire bonder then stitches each pad to the package: a gold or copper wire 15–25 µm across is melted into a ball, pressed and ultrasonically welded to the pad, looped over, and wedge-bonded to a lead, more than ten times a second.
- Mold, mark, singulate. Epoxy compound is forced around die and wires at ~175 °C and cured, the package is laser-marked, and the strip is cut into individual parts.
Beyond wire bonds
Large, fast chips are flip-chip mounted instead: solder bumps or copper pillars on the pads (an IBM idea from the 1960s), and the die flipped face-down onto a substrate, so connections can cover the whole area and not just the edge. Since the late 2010s packaging has become a front line of scaling:
- Chiplets: several smaller dies, each in the best process for its job, in one package. Small dies yield far better (see yield).
- 2.5D: chiplets side by side on a silicon interposer with very fine wiring, the way AI processors sit next to their stacks of high-bandwidth memory.
- 3D stacking: dies stacked and connected by through-silicon vias, as in high-bandwidth memory, or by hybrid bonding, where copper pads on two dies fuse directly at pitches under 10 µm.
Final test, burn-in, and binning
Test again, sort by speed, ship.
Packaging can damage a good die, and some defects only show at temperature, so every packaged part is tested again. A handler carries parts from trays into a socket on the tester, often at both hot and cold temperatures, and runs functional and speed tests. Parts are sorted into bins: identical dies that run at different maximum clocks or voltages become different products, which is why one chip design is sold as several models.
Burn-in runs parts at raised temperature and voltage for hours to flush out "infant mortality," weak parts that would otherwise fail in a customer's first weeks. Failure rate over a product's life follows the bathtub curve: high at first, low and flat through its working life, rising again at wear-out. Burn-in moves the steep early part into the factory.
How transistors wear out
Every transistor degrades a little each time it switches. Reliability engineering keeps that under ten years' worth.
- Dielectric breakdown (TDDB). The gate oxide slowly accumulates defects under its electric field, until they line up into a conducting path and it breaks down. It is tested by stressing capacitors at high voltage and extrapolating to operating conditions.
- Bias temperature instability (BTI). Under gate bias at high temperature, charge trapped at and near the interface shifts the threshold voltage, especially in PMOS (NBTI). It partly recovers when the bias is removed, which makes it notoriously hard to measure.
- Hot carriers (HCI). Electrons accelerated by the high field near the drain gain enough energy to damage the interface, degrading drive current over time. Graded junctions (the extensions) and lower voltages tamed it.
- Electromigration (EM). At current densities of millions of amps per cm², the flowing electrons push metal atoms along, opening voids in wires and vias. Lifetime follows Black's equation, falling with the square of current density and exponentially with temperature: copper and its caps were chosen largely for this.
New processes are qualified by stressing hundreds of parts, typically for a thousand hours at 125 °C and above-nominal voltage, and showing that the projected failure rate over the product's life is acceptable.
Semiconductors: bands, band gaps and doping
Silicon is an insulator that is easy to bribe.
In a crystal, the electrons' allowed energies merge into bands. In silicon, the valence band holds the electrons that bind the atoms together, and it is full. Above it, across a forbidden band gap of 1.12 eV, lies the empty conduction band. Electrons in a full band cannot carry current (there is nowhere for them to move to), so pure silicon at absolute zero is an insulator.
At room temperature, heat kicks a few electrons across the gap: about 1010 per cm³, against 5 × 1022 atoms. Each leaves behind a hole, a missing electron in the valence band that moves like a positive charge. That is intrinsic silicon: a poor conductor whose conductivity rises steeply with temperature.
Doping changes everything. A phosphorus or arsenic atom has five outer electrons to silicon's four; the extra one is bound so loosely (a few hundredths of an eV) that it is free at room temperature. That makes n-type silicon. Boron has three, and grabs an electron from the lattice, making a hole: p-type. One dopant atom per million silicon atoms multiplies the conductivity about a million times.
The dashed line is the Fermi level EF, the energy at which a state has even odds of holding an electron. In intrinsic silicon it sits mid-gap at Ei; n-type doping pulls it toward the conduction band, p-type toward the valence band. Electron and hole densities follow it exponentially:
n = ni e(EF − Ei)/kT p = ni e(Ei − EF)/kT np = ni2
kT is the thermal energy, 25.9 meV at room temperature. Every factor of e in carrier density is one kT of energy. That exponential is the source of the transistor's sharp switching, and of its most stubborn limit.
The pn junction and the depletion layer
Where n-type meets p-type, the free carriers clear out and leave a field behind.
Join n-type and p-type silicon and electrons diffuse from the n side into the p side, holes the other way, and they annihilate. That leaves a thin depletion region stripped of free carriers. What remains there are the fixed, ionised dopant atoms: positive on the n side, negative on the p side. Their charge creates an electric field that pushes back against further diffusion, until the two balance. The bands bend by the built-in potential Vbi, typically 0.7–1 V, which is exactly what it takes to line up the Fermi levels on both sides.
A reverse bias adds to the barrier and widens the depletion region; almost no current flows. A forward bias lowers the barrier, and the current rises exponentially, tenfold for every 60 mV. Every MOSFET contains two junctions, source-to-body and drain-to-body, both normally reverse biased. On the stage, the hatched regions around the source and drain are their depletion layers; the drain's widens as the drain voltage rises.
W = √[ 2εSi(Vbi − V)/q · (NA + ND)/(NAND) ]
How the bands of metal, oxide and silicon line up
Put three materials together and their Fermi levels must agree. Something has to give.
Each material has a work function Φ, the energy needed to lift an electron from its Fermi level out to the vacuum. For silicon it is the electron affinity χ = 4.05 eV (vacuum to the conduction band) plus the distance from there down to the Fermi level, so it depends on doping. Silicon dioxide is an excellent insulator because its gap is huge, about 9 eV, and its conduction band sits 3.1 eV above silicon's: a tall wall for electrons.
Apart, the three materials share a vacuum level. Joined (with the gate wired to the body), their Fermi levels must align. The work-function difference ΦMS = ΦM − ΦS has to be taken up somewhere: partly as a voltage across the oxide, and partly as bending of the silicon's bands near the surface. For an n+ polysilicon gate on p-type silicon, ΦMS is about −1 V, so even at zero gate voltage the p-type surface is pushed toward depletion.
The gate voltage that exactly cancels the difference and flattens the bands is the flat-band voltage:
VFB = ΦMS − Qf / Cox
Qf is any fixed charge sitting in the oxide near the interface, which shifts everything. The stage shows the MOS capacitor: a gate, an oxide, and a body, with no source or drain. It is the heart of the transistor, and the simplest thing to measure.
Accumulation, depletion, inversion
One gate voltage, three completely different surfaces.
Drag the gate voltage and watch the bands bend. The model below solves Poisson's equation for the real device (not a cartoon), and the stage shows the same bias. For the NMOS case, a p-type body:
- Accumulation (gate below flat band). The negative gate attracts holes, which pile up in a thin layer at the surface. The bands bend up.
- Depletion. A positive gate pushes the holes away, uncovering the negative boron ions they had neutralised. The surface becomes a depletion layer, as in a pn junction, and widens as the gate voltage rises. The bands bend down by the surface potential ψs.
- Weak inversion. Once the bands bend by more than φF (the distance from Ei to EF in the bulk), the surface has more electrons than holes. It has been inverted to n-type, though there are still few electrons, rising exponentially with ψs.
- Strong inversion. At ψs = 2φF, the surface is as strongly n-type as the bulk is p-type. Beyond this, almost all the extra gate charge is matched by electrons in a layer only a few nanometres thick, the inversion layer, and the depletion region stops growing. This electron layer is the transistor's channel.
The electrons come from the source and drain in a transistor. In an isolated MOS capacitor they must be generated thermally, which takes time, a fact the C–V measurement exploits.
The threshold voltage
The gate voltage at which the channel appears: the most important number a transistor has.
The threshold is the gate voltage that brings the surface to strong inversion. Add up what the gate has to do: overcome the flat-band offset, bend the bands by 2φF, and support the charge of the depletion region it has uncovered:
VT = VFB + 2φF + √(2qεSiNA·2φF) / Cox with φF = (kT/q) ln(NA/ni)
The process engineer's levers are all in that formula: the body doping NA (the threshold-adjust implant in the wells), the oxide thickness through Cox, and the gate material through VFB. A thinner oxide shrinks the depletion term, which is why thresholds fell as oxides thinned. Chips usually offer several thresholds side by side, low-VT transistors for speed and high-VT ones for low leakage, made with extra implants or different gate metals.
The body effect: biasing the source above the body (VSB) widens the depletion region and raises the threshold, as the dashed curve shows. It matters in stacked transistors, where a source does not sit at ground.
Current versus voltage
The transistor's whole personality, in two plots.
Above threshold, the inversion layer holds a charge of about Cox(VGS − VT) per unit area. A drain voltage makes it drift toward the drain. At small VDS the channel is a resistor whose conductance the gate sets: the linear (or triode) region. As VDS rises, the voltage between gate and channel shrinks toward the drain end, so the channel thins there, until at VDS = VGS − VT it pinches off. Beyond that, extra drain voltage drops across a short depleted stretch near the drain and the current barely rises: saturation.
linear: ID = μCox(W/L)[(VGS − VT)VDS − VDS2/2] saturation: ID = ½μCox(W/L)(VGS − VT)2
That square law is the textbook, long-channel transistor. Real short transistors fall short of it. Electrons cannot go faster than about 107 cm/s however hard they are pushed (velocity saturation), so the current grows more like linearly with overdrive and saturates early. The vertical field from the gate presses electrons against the rough interface and lowers their mobility. And the source and drain resistance steals some of the applied voltage. The model behind these curves includes all three; the label at the end of each curve gives its gate voltage, and the dot is the stage's bias.
Below threshold: 60 millivolts per decade
A transistor never quite turns off, and physics sets how sharply it can try.
Below threshold the channel has few electrons, but not none. They cross from the source by diffusing over an energy barrier that the gate raises and lowers, and the number with enough thermal energy to make it falls off exponentially with the barrier height, by a factor of e per kT. So the current falls exponentially as the gate voltage drops. On a log scale it is a straight line, with a slope called the subthreshold swing:
SS = n (kT/q) ln 10 ≥ 59.6 mV per decade at 300 K, n = 1 + Cdep/Cox
This is sometimes called the Boltzmann tyranny. To cut leakage tenfold, the threshold must rise by at least 60 mV, and more like 70–90 mV in real transistors (n > 1, because the gate shares control of the surface with the body). A transistor that must switch between on and off with a good Ion/Ioff ratio of 104–106 therefore needs several hundred millivolts of headroom between its threshold and its supply. That is why supply voltages stopped falling at around 0.7–1 V (see the end of Dennard scaling). Heat makes it worse: the swing grows with temperature, and leakage climbs steeply in a hot chip.
Deeper: ways around 60 mV
The limit holds for any switch that works by lifting a barrier over thermally distributed carriers. Research devices try to cheat it: tunnel FETs, where carriers tunnel through a band edge instead of hopping over it; negative-capacitance FETs, with a ferroelectric layer that amplifies the gate voltage; and nano-mechanical relays. None has yet matched silicon's drive current at a steep slope.
Short-channel effects: when the drain takes over
Shrink the gate far enough and the drain starts controlling the channel too.
In a long transistor, the gate alone decides the height of the barrier between source and channel. As the gate shortens, the drain's depletion region reaches a larger fraction of the way across, and the drain's field starts to lower the barrier itself:
- Threshold roll-off: the threshold falls as the gate gets shorter, so small variations in gate length become large variations in leakage.
- DIBL (drain-induced barrier lowering): the threshold falls as the drain voltage rises. Measured in mV of threshold shift per volt on the drain.
- Degraded swing: the gate's grip weakens, so the subthreshold slope steepens past 60 mV/decade toward 100 and beyond.
- Punch-through: in the limit, the source and drain depletion regions merge below the surface and current flows where the gate has no control at all.
A useful rule: the gate keeps control when the channel is longer than about five to six natural lengths λ, a length set by how thick the oxide is and how deep the silicon under the gate reaches. For a planar transistor λ grows with the oxide thickness and the depletion depth; for a thin body gated on several sides it shrinks with the body thickness and the number of gates:
planar: λ ≈ √(εSi/εox · tox · Wdep) double gate: λ ≈ √(εSi/(2εox) · tox · tSi)
Planar transistors fought back with thinner oxides, shallower junctions, heavier channel doping and halos, but heavy doping costs mobility and adds junction leakage. At around 22 nm the only good move left was to make the silicon body itself thin and wrap the gate around it: the FinFET, and later gate-all-around. The chart shows why, using the same model for all three.
Two more short-channel troubles: GIDL (gate-induced drain leakage), where the strong field where gate overlaps drain lets electrons tunnel straight across the band gap, adding leakage in the off state; and hot carriers.
CMOS: why every chip uses both kinds
Pair an NMOS with a PMOS and, except while switching, no current flows.
The cross-section is an inverter. The PMOS connects the output to the supply and the NMOS connects it to ground, and the same input drives both gates. Input high: the NMOS is on and the PMOS off, so the output is pulled to ground. Input low: the reverse. In either steady state one transistor is off, so no current flows from supply to ground. Power is spent only while switching, charging and discharging the capacitance of the wires and gates:
Pdynamic = α C VDD2 f plus leakage
Frank Wanlass invented complementary MOS at Fairchild in 1963. It was slower and more complicated to make than single-type NMOS, and for two decades it was used mainly where power mattered most, such as watches. As chips grew to hundreds of thousands of transistors, NMOS logic, which burns current whenever its output is low, became too hot, and CMOS took over in the mid-1980s. Holes are slower than electrons, so a PMOS is usually made wider than its NMOS partner to balance them; try the width ratio above.
The four-point probe
The workhorse measurement of a doped or metal layer: push current through two needles, read voltage on two others.
Four spring-loaded needles in a line, about a millimetre apart, press onto the wafer. A known current passes between the outer two. The inner two measure the voltage drop, drawing essentially no current themselves, so the resistance of the needles and their contacts drops out. For a layer much thinner than the probe spacing on a wafer much wider than it, the geometry works out to a constant (Valdes, 1954; Smits, 1958):
Rs = (π / ln 2) · V/I ≈ 4.532 · V/I (ohms per square) for a thick sample: ρ = 2πs · V/I
Sheet resistance Rs is the resistance of any square of a film, whatever its size, and for a doped layer it is roughly 1/(qμ × dose), so it is a sensitive check on implant dose, energy and anneal all at once. Fabs run monitor wafers through implanters and furnaces and map them at 49 sites in rings, looking at the mean and the uniformity:
The same tool measures metal films (thickness = resistivity / Rs) and silicide. Related techniques: eddy-current gauges for metals without touching; thermal-wave tools that sense implant damage on product wafers before annealing; van der Pauw and Greek-cross test structures for sheet resistance in the scribe line; and spreading resistance or SIMS for profiles with depth.
Measuring a transistor: I–V parameters
Sweep the gate, sweep the drain, extract a dozen numbers.
A parametric analyzer with four source-measure units (one per terminal) sweeps the gate at a low drain voltage (50 mV, the linear region) and again at the supply voltage, and sweeps the drain at a few gate voltages. Each measures current down to femtoamps. Kelvin connections (separate force and sense wires) keep cable resistance out of the result. From those curves:
- Threshold voltage, two common ways: the constant-current method (the gate voltage where the current reaches, say, 100 nA × W/L), fast and used in production; and linear extrapolation (the tangent at peak transconductance extended to zero current, minus VDS/2), closer to the textbook definition. They differ by tens of millivolts, so a spec must say which.
- Transconductance gm = ∂ID/∂VGS: gain, and, through gm = μCox(W/L)VDS, a window on mobility.
- Subthreshold swing, from the slope of log ID.
- DIBL: the difference between linear and saturated thresholds divided by the difference in drain voltage.
- Ion (both terminals at the supply) and Ioff (gate at zero, drain at the supply), the pair every technology is judged by.
- Series resistance: by measuring transistors of several gate lengths and extrapolating the total resistance to zero length.
Capacitance–voltage: reading an oxide without seeing it
Sweep a MOS capacitor's gate voltage and its capacitance traces out the oxide, the doping and the interface.
Measure a MOS capacitor's capacitance with a small AC signal while sweeping its DC gate voltage. In accumulation the charges sit right at both faces of the oxide, and the capacitance is just the oxide's, Cox = εox/tox, which gives the thickness directly. In depletion the depletion layer adds a second capacitor in series and the total falls. In inversion the curve depends on frequency. At low frequency, electrons in the inversion layer can follow the signal and the capacitance climbs back to Cox. At 1 MHz they cannot be generated fast enough, the depletion layer is stuck at its maximum width, and the capacitance stays at a minimum that reveals the doping.
- Oxide thickness from Cmax; doping from Cmin (or from the slope of 1/C2 in depletion); flat-band voltage from where the curve sits, which gives the work-function difference and any fixed charge (slide it above and watch the curve shift sideways).
- Interface traps stretch the curve out and separate the low- and high-frequency curves; comparing them gives their density.
- Mobile ions (sodium again): heat the capacitor under bias, measure again, and any ions that drifted shift the curve.
At 1–2 nm, C–V gets harder. Tunnelling current swamps the capacitance signal, and the measured maximum is smaller than the oxide's own, because the inversion charge sits about a nanometre below the interface (a quantum effect) and poly gates deplete. That is why a thin oxide has two thicknesses: the physical one, and a slightly larger electrical one (CET) that sets the drive current. Production fabs also measure oxides without contacts, by spraying a known charge onto the surface with a corona discharge and reading the surface voltage with a Kelvin probe.
Inline metrology: measuring as you go
Most of a fab's tools exist to make things; a large minority exist only to check them.
Electrical tests come at the end. During the three months before, wafers are measured after nearly every important step, usually on a sample of wafers and sites, with results fed into statistical process control and often straight back into the tools (run-to-run control).
| What | How | After |
|---|
| Film thickness | Spectroscopic ellipsometry and reflectometry (how a film changes reflected light's polarisation and colour); X-ray reflectometry and XPS for the thinnest films | Every deposition, oxidation, CMP |
| Line width (CD) | CD-SEM, a scanning electron microscope that measures from above; scatterometry (fitting the diffraction of light from gratings to a model of their profile) | Lithography and etch |
| Overlay | Optical measurement of how far one layer's marks sit from the last's, to a nanometre or two | Every lithography step |
| Defects | Bright- and dark-field optical inspection compares each die with its neighbours; e-beam inspection finds electrical defects by voltage contrast; review SEMs image and classify what was found | Most steps, sampled |
| Sheet resistance | Four-point probe, eddy current | Implant, anneal, metal, silicide |
| Dose | Thermal-wave (modulated reflectance), on product wafers | Implant |
| Stress, flatness | Wafer bow by interferometry | Films, CMP |
| Composition | X-ray fluorescence; SIMS on monitors | Silicide, high-k, doping |
And when something looks wrong, a focused ion beam cuts a cross-section and a transmission electron microscope images it atom by atom: the real version of the drawing on this page.
Lithography
Printing with light, at a resolution well below the light's own wavelength.
Every pattern on the chip starts as photoresist. A track coats the wafer with a few hundred nanometres of resist (over an anti-reflective layer), bakes it, and hands it to a scanner, which projects the pattern of a mask (reticle) onto it, shrunk four times through a lens of extraordinary precision. The scanner exposes one field (up to 26 × 33 mm, a few chips) by sweeping mask and wafer past a slit in opposite directions, then steps to the next. Modern resists are chemically amplified: each absorbed photon releases an acid that, during a post-exposure bake, catalyses hundreds of reactions that make the resist soluble. A developer then washes the exposed resist away.
The smallest half-pitch one exposure can print follows the Rayleigh criterion:
R = k1 λ / NA depth of focus ≈ k2 λ / NA2
λ is the wavelength, NA the numerical aperture of the lens (how wide a cone of light it collects), and k1 a measure of how cleverly the process squeezes out resolution: phase-shifting masks, off-axis illumination, and optical proximity correction, which pre-distorts mask shapes so that they print as intended. The physical floor for one exposure is k1 = 0.25. Each lever has its own history.
Two numbers are checked after every lithography step: the width of the printed lines (CD, by CD-SEM), and overlay, how well this layer lines up with the ones below. A leading-edge scanner aligns layers to within a nanometre or two across a 300 mm wafer.
Etching
Removing exactly what the resist does not cover, straight down, and stopping in time.
Wet etching dissolves material in a liquid: hydrofluoric acid for oxide, hot phosphoric acid for nitride. It is cheap, gentle and highly selective, but isotropic: it eats sideways as fast as down, undercutting the mask. That is fine for stripping whole films, useless for 50 nm lines.
Plasma (dry) etching puts the wafer in a low-pressure gas lit by radio-frequency power. The plasma makes reactive radicals, which form volatile compounds with the surface (silicon + chlorine → SiCl4; oxide + fluorocarbons → SiF4 and CO), and ions, which a bias voltage accelerates straight down onto the wafer. The ions drive the reaction where they hit, on the floors of features, while the sidewalls, struck only glancingly and coated with a thin protective polymer, barely etch. The result is anisotropic etching: vertical walls. This is reactive ion etching.
- Selectivity: how much faster the target etches than the layer beneath. The gate etch must stop on 1.6 nm of oxide after cutting 100 nm of poly.
- Endpoint: optical emission spectroscopy watches the plasma's glow change as one material clears and the next appears.
- Loading and aspect ratio: dense areas, open areas and deep, narrow holes all etch at different rates, which recipes must balance.
- Atomic layer etching: alternating a self-limiting surface reaction with a gentle ion pulse removes one atomic layer per cycle, for the most critical modern steps.
Growing and depositing films
Every layer on the chip is grown from the silicon or laid down on it, a few atoms to a few micrometres at a time.
- Thermal oxidation grows oxide from the silicon itself, consuming it. It makes the best interfaces in the business, so gate oxides and liners are grown (see thermal processing).
- Chemical vapour deposition (CVD) reacts gases on a hot surface: silane for polysilicon, dichlorosilane and ammonia for nitride, TEOS for oxide. Low-pressure furnaces (LPCVD) coat a hundred wafers at once, uniformly; plasma-enhanced CVD (PECVD) works at 300–400 °C, cool enough for after the metal is in; high-density-plasma CVD deposits and sputters at once to fill gaps.
- Atomic layer deposition (ALD) alternates two gases, each of which reacts with the surface until it is covered and then stops. One cycle lays down a fraction of a nanometre, perfectly evenly over any topography. High-k gate dielectrics are made this way (HfCl4 and water for HfO2).
- Physical vapour deposition (PVD, sputtering) knocks atoms off a metal target with argon ions; they fly in straight lines onto the wafer. Directional, so it coats tops better than deep sidewalls; ionised PVD steers the metal ions down into trenches. Used for barriers, seeds, nickel and aluminium.
- Epitaxy grows new single crystal on a crystal: the epi layer on starting wafers, and the SiGe and doped-silicon source/drains of strained and FinFET transistors.
- Electroplating for copper wiring (see damascene).
The key property of a deposited film, beside thickness and composition, is conformality: does it coat a vertical wall as thickly as a flat top? The spacer process on the stage depends on a fully conformal film.
Ion implantation
Doping by firing atoms into the wafer, counted one by one.
An implanter ionises a dopant gas (BF3, PH3, AsH3), extracts the ions, and sends the beam through a magnet that bends each mass by a different amount, so only the wanted species gets through. The ions are accelerated to between a few hundred eV and several MeV and scanned across the wafer. The dose (ions per cm²) is counted exactly by measuring the beam's charge in Faraday cups, which is why implantation replaced furnace diffusion for nearly all doping in the 1970s. The energy sets the depth.
Each ion slows by collisions with nuclei and electrons and comes to rest at a random depth, roughly Gaussian about a projected range Rp with a spread ΔRp. Light boron goes deep; heavy arsenic stops shallow. Two details matter in practice. Along the open directions of the crystal lattice, ions can channel deep before they hit anything, so wafers are tilted about 7° off axis, or the surface is pre-amorphised. And the collisions leave the lattice badly damaged, so every implant is followed by an anneal, which also spreads the profile, as the curve shows.
Fabs run three families of implanters: high-current, for source/drain doses of 1015/cm² and up; medium-current, for precise lower doses, including the tilted halo implants; and high-energy, up to several MeV, for deep wells.
Oxidation and annealing
Heat grows oxides, activates dopants and heals damage, and every second of it moves the dopants.
Silicon's great advantage over every other semiconductor is its oxide: SiO2 grows on it simply by heating in oxygen or steam, and the interface between them is nearly perfect, with fewer than one defect per hundred thousand surface atoms after a hydrogen anneal. Bruce Deal and Andrew Grove (later Intel's CEO) worked out the kinetics in 1965:
x2 + A x = B(t + τ)
Thin oxides grow linearly, limited by the reaction at the interface (rate B/A); thick ones parabolically, limited by oxygen diffusing through the oxide already there (B). Steam oxidises several times faster than dry oxygen, so thick oxides are grown wet and gate oxides dry. Deal–Grove underestimates the very first few nanometres, which grow faster than it predicts, so thin gate oxides are tuned empirically in rapid thermal tools.
Annealing heats without growing anything, to activate implants, repair damage, densify films or form silicides. The tools have moved to ever shorter times: tube furnaces (100+ wafers, minutes to hours), rapid thermal processors (one wafer, lamps, seconds, and "spikes" with no time at peak), flash lamps (milliseconds) and lasers (microseconds). The thermal budget, roughly the sum of every step's diffusion length squared, √(D t), had to shrink with the junctions.
Chemical-mechanical polishing
The step that made modern chips possible by making each layer flat again.
A wafer, face down in a carrier, is pressed against a rotating polyurethane pad flooded with slurry: abrasive particles of silica, ceria or alumina in a chemistry that softens the surface (oxidisers for metals, a high pH for oxide). Chemistry weakens the top layer, abrasion carries it off. Removal follows Preston's 1927 law for polishing glass: rate ∝ pressure × speed. Because high points feel more pressure, they polish faster, and the surface flattens.
IBM brought CMP into chipmaking in the late 1980s. Without it, every layer's topography would pile onto the last, the lithography would lose focus, and copper damascene and trench isolation would not work at all. Its quirks:
- Dishing: soft material in a wide feature (copper in a broad wire, oxide in a wide trench) polishes into a shallow dish.
- Erosion: dense arrays of features thin out as a whole.
- Both depend on the local pattern density, so designs are filled with electrically useless dummy shapes to even it out.
- Endpoint is detected through windows in the pad (reflected light) or from the motor current changing as one material clears.
Moore's law
An observation from 1965 that became a fifty-year industrial plan.
In April 1965 Gordon Moore, then at Fairchild, noted in Electronics that the number of components on the most cost-effective chip had doubled every year since the integrated circuit's invention, and predicted it would continue for a decade. In 1975 he revised the pace to a doubling every two years. The industry then organised itself around the prediction: equipment makers, chip designers and fabs planned their generations to land on it, in the form of a roadmap (ITRS, now IRDS).
The 4004 of 1971 had 2,300 transistors; Nvidia's Rubin GPU of 2026 has 336 billion across two dies, a factor of about 108 in 55 years, close to a doubling every two years. The stage shows the planar transistor that carried most of that journey. The rest of this group is how it kept shrinking: what each generation changed, and why the transistor eventually had to change shape.
Dennard scaling, and the day it stopped
For thirty years, shrinking made transistors faster and cheaper with no penalty in power. Then it didn't.
In 1974 Robert Dennard and colleagues at IBM (Dennard had also invented the one-transistor DRAM cell) showed how to shrink a MOSFET properly. Scale every dimension, including the oxide, by 1/κ; scale the voltage by 1/κ; raise the doping by κ. Then the fields inside stay the same, each transistor gets κ times faster and uses κ² times less power, and κ² times more fit in the same area, so power per area stays constant. Each generation (κ ≈ 1.4) gave twice the transistors, 40% more speed and the same power density. Free performance.
It held, roughly, until about 2005. The weak link is the 60 mV/decade limit. Voltage can only fall if the threshold falls with it, and every 60–90 mV off the threshold multiplies the leakage tenfold. By the 90 nm generation, leakage was a large share of chip power, and the gate oxide, at 1.2 nm, was leaking as well. Supply voltages stalled near 1 V. With voltage stuck, power density rose with every shrink, until processors hit the roughly 100 W per chip that air cooling can remove. Clock speeds stopped near 3–4 GHz, and the industry turned to multiple cores, specialised accelerators, and power-gating of whatever is idle ("dark silicon").
Shrinking continued; what ended was shrinking for free. Since then each generation has needed a new material or structure to deliver its gains.
What "7 nm" means (not much)
Node names once measured something. Now they are brand names on a schedule.
Through the 1990s a process "node" named a real feature: roughly the gate length, or half the pitch of the densest lines. Then gate lengths shrank faster than the node names (a 130 nm process had 60–70 nm gates), and from the FinFET era onward the opposite: names kept falling by about 0.7× per generation while the physical dimensions slowed. A "3 nm" transistor has a gate about 16 nm long and its gates sit about 48 nm apart. In 2021 Intel renamed its 10 nm process "Intel 7" to match competitors' naming.
More honest measures are the contacted gate pitch (centre-to-centre spacing of transistors) and the minimum metal pitch, whose product sets the size of a logic cell, or simply transistors per mm². Those have kept shrinking, now more slowly, and increasingly helped by design tricks (fewer fins per transistor, stacking, backside power) rather than by smaller features alone.
Strained silicon, 2003
Squeeze or stretch the crystal, and electrons and holes move faster.
Mobility depends on the shape of silicon's bands, and mechanical strain reshapes them: it splits apart energy valleys that are normally equal, so carriers sit in the ones with lighter effective mass and scatter less. Compressing a PMOS channel along the current flow speeds up holes; stretching an NMOS channel speeds up electrons.
Intel's 90 nm process (2003) was the first to do it deliberately in volume. For PMOS, the source and drain were etched out and regrown epitaxially as silicon-germanium; germanium atoms are about 4% larger than silicon's, so the SiGe pushes in on the channel from both sides, as the 3D model shows. For NMOS, a silicon nitride capping layer deposited under tension pulls the channel along. Others used dual stress liners (the contact etch stop layer, deposited tensile over NMOS and compressive over PMOS). Hole mobility rose by around half, and drive currents by 10–25%, at almost no cost in area.
Strain engineering has been in every leading-edge process since: embedded SiGe got richer in germanium, stress was "memorised" into gates, and FinFET and nanosheet source/drains are strained epitaxy by design. The lab has a strain switch.
High-k dielectrics and metal gates, 2007
The gate oxide could not get any thinner, so it was replaced with something that could be thicker.
By the 65 nm generation, SiO2 gate oxides were about 1.2 nm thick, five atomic layers, and electrons were tunnelling straight through them. Tunnelling current rises about tenfold for every 0.2 nm thinner, so another shrink was impossible.
What the transistor needs is not a thin oxide but a large capacitance, C = kε0/t. A material with a higher dielectric constant k gives the same capacitance at a greater physical thickness. Thickness is quoted as equivalent oxide thickness, EOT = t × 3.9/k: hafnium oxide (k ≈ 20–25) can be about five times thicker than SiO2 at the same EOT, and a thicker barrier leaks exponentially less:
Making it work took a decade of research. Hafnium oxide on silicon traps charge and scatters electrons, so a thin SiO2 interface layer (~0.5 nm) stays underneath. Polysilicon gates pin their Fermi level on high-k and push the thresholds out of range, so the gates became metals with tuned work functions, one for NMOS and one for PMOS, which also ended poly depletion. Intel chose gate-last, or replacement metal gate: build the transistor with a dummy polysilicon gate, finish the hot steps, then pull the dummy out and fill the trench with high-k and metals. That is why the high-k in the model lines a U-shaped trench. Intel's 45 nm process (Penryn, late 2007) cut gate leakage more than 25-fold for NMOS against its 65 nm process; Gordon Moore called it the biggest change in transistor technology since polysilicon gates arrived in the late 1960s.
Lithography: from mercury lamps to tin plasma
Every lever in R = k1λ/NA was pulled, one after another.
- Shorter wavelengths. Mercury lamp lines g (436 nm) and i (365 nm) through the 1980s and early 1990s, then excimer lasers: KrF at 248 nm from the mid-1990s, ArF at 193 nm from about 2003.
- Higher NA. Lenses grew to collect wider cones of light, approaching NA 0.93 in air. Then immersion (around 2006–7): a film of water between lens and wafer, with refractive index 1.44, pushed NA to 1.35.
- Lower k1. Resolution-enhancement tricks pushed toward the 0.25 floor. Below it, multiple patterning: print every other line, then the ones between (litho-etch-litho-etch), or use spacers grown on printed lines as the pattern itself (self-aligned double and quadruple patterning). 7 nm-class chips were printed with 193 nm light in four passes for their tightest layers.
- EUV, 13.5 nm. No lens transmits it and air absorbs it, so everything runs in vacuum with mirrors of alternating molybdenum and silicon layers, each reflecting about 70%. The light comes from droplets of molten tin, about 50,000 a second, each hit by a high-power CO2 laser to make a plasma. After two decades of development it entered volume production in 2019, at Samsung and TSMC's 7 nm-class processes.
- High-NA EUV, NA 0.55, uses anamorphic optics that shrink one direction more than the other. Intel finished acceptance testing of ASML's production high-NA scanner (EXE:5200B) in December 2025, for its 14A process, with volume production expected around 2028.
ASML in the Netherlands is the only maker of EUV scanners; each costs hundreds of millions of dollars and ships in several cargo planes.
Wires at the limit
Transistors get better as they shrink. Wires get worse.
A wire's delay scales with its resistance times its capacitance. Shrink a wire's width and height together and its resistance per length rises with the square of the shrink, while its capacitance to its neighbours stays about the same. So the RC delay of a millimetre of wire grows each generation, even as transistors speed up.
The industry answered with materials: copper for aluminium in 1997–98, then low-k and porous ultra-low-k dielectrics, and air gaps between the tightest wires. But at widths of a few tens of nanometres copper itself runs into trouble. Its electrons travel about 40 nm between collisions in bulk metal, so in thinner wires they scatter off surfaces and grain boundaries and the resistivity climbs. And the barrier, which cannot shrink much below 2–3 nm, takes up a growing share of the trench. Cobalt (used by Intel at 10 nm for the lowest levels) and ruthenium and molybdenum, which have short electron paths and need little or no barrier, are taking over the tightest levels. Backside power attacks the same problem from another side.
The FinFET, 2011
Stand the channel on its edge and wrap the gate over it.
A planar transistor's gate sits on top of a channel that sits on a deep slab of silicon. Below the surface the gate's grip weakens, and the drain's field leaks in underneath (see short-channel effects). The cure is a body so thin that no part of it is far from the gate. In a FinFET, the channel is a thin vertical fin of silicon, about 8 nm wide at Intel's 22 nm, with the gate wrapped over its top and both sides.
- Electrostatics. Gated on three sides, the natural length shrinks with the fin width, so subthreshold swing returns to 65–70 mV/decade and DIBL drops severalfold. Thresholds and supply voltages could fall again: Intel's 22 nm ran at 0.8 V.
- No heavy doping. The fin needs almost none, so mobility improves, and transistors vary less, since there are no random dopant atoms to be unevenly scattered.
- Width in fins. Drive current is set by the fin's height and the number of fins, which come in whole numbers. Taller fins (from ~34 nm at 22 nm to over 50 nm later) bought current without area.
The idea came from Hitachi's "DELTA" transistor (1989) and Chenming Hu, Tsu-Jae King and Jeffrey Bokor's group at Berkeley, who named it FinFET in 1999. Intel shipped it first, as "tri-gate," in Ivy Bridge processors in 2012; TSMC and Samsung followed in 2015. Turn on Cut open at the bottom: the cut runs through the gate, across the fins, so you see each fin wrapped in high-k and metal.
Gate-all-around nanosheets, 2022–2025
Lay the fin down, slice it into sheets, and wrap the gate all the way around each one.
Fins could not get much thinner or taller. The next step puts gate on the fourth side: a stack of horizontal silicon nanosheets, each about 5 nm thick, every one completely surrounded by gate. Electrostatic control is the best possible, so gates can be shorter, and unlike fins the sheets' width can be chosen freely, wide for drive or narrow for density.
Making it is a feat of selective chemistry. The wafer starts with an epitaxial stack of alternating silicon and silicon-germanium layers, patterned into fins. A dummy gate is formed over them, spacers and source/drain epitaxy follow, and the dummy gate is removed. An etch that dissolves SiGe but not silicon then hollows out the gate region, leaving the silicon sheets suspended like the rungs of a ladder (the channel release). ALD coats every surface of every sheet with high-k and metal. Before that, the SiGe ends under the spacers are recessed and refilled with dielectric inner spacers, so the gate does not short to the source and drain.
Samsung shipped the first, which it calls MBCFET, at 3 nm in 2022. TSMC's N2 entered volume production in the fourth quarter of 2025, and Intel's 18A ("RibbonFET") launched in Core Ultra series 3 laptop processors in January 2026. With Cut open, the model shows three sheets ringed by gate.
Backside power delivery
Power and signals had shared one side of the wafer for sixty years. Now power comes in from the back.
Every transistor needs power from the thick top metal, carried down through every wiring level, losing voltage along the way (IR drop), and taking up routing tracks that signals need. Backside power moves the power network underneath. The front side is built as usual, then bonded face-down onto a carrier wafer; the original substrate is ground and polished away until the transistors are reached from behind; and power wires and contacts are built on what used to be the bottom. Signal wiring keeps the whole front side.
- Intel's PowerVia, in its 18A process, reached products in 2026.
- TSMC's Super Power Rail, contacting the source and drain directly from the back, is in its A16 process, scheduled for volume production in the fourth quarter of 2026, with products expected in 2027. TSMC projects 8–10% more speed or 15–20% less power than N2P.
The model shows a nanosheet transistor with signal wiring above, a bonded carrier wafer on top, the substrate gone, and thick power wiring below.
What comes next
Stack the transistors themselves.
- CFET (complementary FET), shown on the stage: the NMOS nanosheets built directly on top of the PMOS ones, sharing a gate, so an inverter takes the footprint of one transistor. Imec, Intel, TSMC and Samsung have shown working stacks; imec's roadmap puts them in production in the early 2030s. A forksheet, with NMOS and PMOS sheets on either side of a thin dielectric wall, is a possible step before.
- 2D-material channels: single-molecule-thick semiconductors such as MoS2 or WSe2, thin enough to keep gate control at gate lengths below 10 nm, where silicon sheets lose mobility.
- 3D integration: logic and memory stacked by hybrid bonding at ever finer pitch, and transistor layers built sequentially on top of one another.
- New wires: ruthenium, molybdenum, and wires etched again rather than inlaid, now that the metals can be.
And beyond the transistor: spintronics, photonics, and the steep-slope switches that would beat 60 mV/decade. Each has been the future for a while. The MOSFET, at sixty-odd years old, remains the present.
Transistor lab
Build a transistor from any era, change one thing at a time, and watch the numbers move.
Start from a preset, then turn the knobs. Everything recomputes from the device physics: the threshold from the doping, oxide and gate; the current from mobility, velocity saturation and series resistance; the short-channel effects from the natural length; the gate leakage from tunnelling through the stack. The stage shows the same device, and the sliders at the bottom set its bias.
Things to try
- Shrink the gate on the 130 nm preset to 25 nm and watch the threshold collapse and the off current climb: short-channel effects. Then switch to FinFET at the same length.
- Thin the oxide below 1.2 nm of SiO2 and watch the gate leakage overtake the off current. Then switch the dielectric to HfO2 at the same EOT.
- Heat it to 400 K (127 °C). The swing worsens, the threshold drops, leakage rises about twentyfold, and the drive current falls with the mobility.
- Compare eras: pin the 1985 preset, then load the 2025 one. Drive current per micrometre has risen about tenfold at a seventh of the voltage.
- Flip to PMOS and see what slower holes cost, then add strain.
About the models
A teaching model, not a process simulator. Everything runs in your browser.
- The process (
media/transistors/process.js) is a representative planar CMOS flow of the 130–90 nm era, simplified: one slice through an inverter, no well taps, gate contacts out of the plane, one pass of each lithography step shown as its developed result, and seven or so of the hundreds of real steps per module. Each step only sets flags; the drawing is computed from one table of dimensions, schematic or true to a 90 nm-class process. The steps, tools, conditions and checks are typical published values, not one company's recipe.
- The MOS capacitor (
physics.js, mosCap) solves 1D Poisson–Boltzmann exactly for a uniformly doped body: surface potential, band diagram, charges, and low- and high-frequency C–V. No quantum confinement, interface traps or incomplete ionisation. Band offsets and dielectric constants follow Robertson's compilations; ni follows Misiakos and Tsamakis (9.7 × 109 cm−3 at 300 K).
- The transistor is a compact model in the EKV style, smooth from subthreshold to saturation, with a universal mobility curve fitted to Takagi et al. (1994), Coulomb scattering, uniaxial strain and fin-sidewall orientation as multipliers, velocity saturation with modest overshoot at short lengths, series resistance, and short-channel effects (threshold roll-off, DIBL, swing degradation) from the natural length of planar, double-gate and gate-all-around geometries (after Liu et al., 1993, and Colinge). Planar doping stands in for real halo and retrograde profiles. The presets' channel doping or work function was tuned to each era's typical off-state leakage; drive currents then land within about 15% of Intel's published 90, 45 and 22 nm figures.
- Gate leakage is a WKB-style tunnelling estimate through each layer of the stack, normalised to about 100 A/cm² for 1 nm of SiO2 at 1 V. It reproduces the familiar tenfold rise per 2 Å, but the absolute values are rough.
- Implant profiles are Gaussians with LSS-type ranges (Gibbons' tables), broadened by intrinsic diffusion; sheet resistance uses Caughey–Thomas mobility and a crude activation model. Oxidation uses the Deal–Grove constants. Yield uses the standard Poisson and Murphy models.
- The 3D scenes are illustrative. Proportions are compressed (the ingot is drawn shorter, the wafer thicker, wires wider), and the transistor models show structure, not exact dimensions.
The physics and process files load in node, so the numbers can be checked from the command line: require('./knowledge/media/transistors/physics.js').device(...).metrics().
Sources
Books
- S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (Wiley, 2007).
- Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed. (Cambridge, 2009).
- J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling (Prentice Hall, 2000).
- D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. (Wiley, 2006): four-point probe, C–V, contact resistance, threshold extraction.
- J.-P. Colinge, ed., FinFETs and Other Multi-Gate Transistors (Springer, 2008): natural length.
Papers
- G. E. Moore, "Cramming more components onto integrated circuits," Electronics 38(8), 1965; "Progress in digital integrated electronics," IEDM 1975.
- R. H. Dennard et al., "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits 9(5), 1974.
- B. E. Deal and A. S. Grove, "General relationship for the thermal oxidation of silicon," J. Appl. Phys. 36, 3770 (1965).
- W. Kern and D. A. Puotinen, "Cleaning solutions based on hydrogen peroxide for use in silicon semiconductor technology," RCA Review 31, 187 (1970).
- W. C. Dash, "Growth of silicon crystals free from dislocations," J. Appl. Phys. 30, 459 (1959).
- L. B. Valdes, "Resistivity measurements on germanium for transistors," Proc. IRE 42, 420 (1954); F. M. Smits, "Measurement of sheet resistivities with the four-point probe," Bell Syst. Tech. J. 37, 711 (1958).
- Z.-H. Liu et al., "Threshold voltage model for deep-submicrometer MOSFETs," IEEE Trans. Electron Devices 40(1), 1993.
- S. Takagi et al., "On the universality of inversion layer mobility in Si MOSFET's," IEEE Trans. Electron Devices 41(12), 1994.
- K. Misiakos and D. Tsamakis, "Accurate measurements of the silicon intrinsic carrier density from 78 to 340 K," J. Appl. Phys. 74, 3293 (1993).
- J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vac. Sci. Technol. B 18, 1785 (2000); "High dielectric constant oxides," Eur. Phys. J. Appl. Phys. 28, 265 (2004).
- S. E. Thompson et al., "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices 51(11), 2004.
- K. Mistry et al., "A 45nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," IEDM 2007.
- C. Auth et al., "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," VLSI Symposium 2012.
- D. Hisamoto et al., "A fully depleted lean-channel transistor (DELTA)," IEDM 1989; X. Huang et al., "Sub 50-nm FinFET: PMOS," IEDM 1999.
- J. R. Black, "Electromigration: a brief survey and some recent results," IEEE Trans. Electron Devices 16(4), 1969.
Recent milestones (checked October 2026)